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71M6543F/71M6543G Data Sheet
Wake Enable
Name Location
Wake Flag
Name Location
De-bounce
Description
Always Enabled
Always Enabled
Always Enabled
WF_OVF
WF_CSTART
WF_BADVDD
28B0[4]
28B0[7]
28B0[2]
No
No
No
Wake after WD reset.
Wake after cold start - the first
application of power.
Wake after insufficient VBAT
voltage.
* This pin is sampled every 2 ms and must remain high for 64 ms to be declared a valid high level. This pin is high-
level sensitive.
Table 64: Wake Bits
Name
EW_DIOR
EW_DIO52
EW_DIO55
WAKE_ARM
EW_PB
EW_RX
WF_DIO4
WF_DIO52
WF_DIO55
WF_TMR
WF_PB
WF_RX
WF_RST
WF_RSTBIT
WF_ERST
WF_CSTART
WF_BADVDD
Location
28B3[2]
28B3[1]
28B3[0]
28B2[5]
28B3[3]
28B3[4]
28B1[2]
28B1[1]
28B1[0]
28B1[5]
28B1[3]
28B1[4]
28B0[6]
28B0[5]
28B0[3]
28B0[7]
28B0[2]
RST
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
WK
–
–
–
–
–
–
–
–
–
–
–
–
–
Dir
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
Description
Connects SEGDIO4 to the WAKE logic and permits
SEGDIO4 rising to wake the part. This bit has no effect
unless SEGDIO4 is configured as a digital input.
Connects DIO52 to the WAKE logic and permits DIO52
high level to wake the part. This bit has no effect unless
DIO52 is configured as a digital input.
Connects DIO55 to the WAKE logic and permits DIO55
high level to wake the part. This bit has no effect unless
DIO55 is configured as a digital input.
Arms the WAKE timer and loads it with the value in
WAKE_TMR ( I/O RAM 0x2880 ) register. When SLP or
LCD mode is asserted by the MPU, the WAKE timer
becomes active.
Connects the PB pin to the WAKE logic and permits PB
high level to wake the part. PB is always configured as
an input.
Connects the RX pin to the WAKE logic and permits
RX rising to wake the part. See 3.4.1 for de-bounce
issues.
SEGDIO4 flag bit. If SEGDIO4 is configured to wake
the part, this bit is set whenever SEGDIO4 rises. It is
held in reset if SEGDIO4 is not configured for wakeup.
SEGDIO52 flag bit. If SEGDIO52 is configured to wake
the part, this bit is set whenever SEGDIO52 is a high
level. It is held in reset if SEGDIO52 is not configured
for wakeup.
SEGDIO55 flag bit. If SEGDIO55 is configured to wake
the part, this bit is set whenever SEGDIO55 is a high
level. It is held in reset if SEGDIO55 is not configured
for wakeup.
Indicates that the Wake timer caused the part to wake up.
Indicates that the PB pin caused the part to wake.
Indicates that RX pin caused the part to wake.
Indicates that the RST pin, E_RST pin, RESET bit ( I/O
RAM 0x2200[3]) , the cold start detector, or low voltage
on the VBAT pin caused the part to reset.
*See Table 65 for details.
82
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